IMEC Belgium

Role in the TEMPO consortium

Imec is the project coordinator in this project.

On a technical level, imec will explore technology, circuit, architecture and alogorithm co-optimization for neuromorphic applications. More specifically, imec will leverage its process technology expertise in MRAM, 3D integration and TFT device to enable energy efficient neural network accelerators. CMOS basewafers implemented in standard foundry technolgy will be used as a platform to optimize MRAM devices, fabricated in imec’s cleanroom, for use in DNN accelerators. The circuit and architecture design will be done for both pure digital as well as analog/mixed signal computation using resistive memory elements for multiply-accumulate operations. Imec will evaluate the impact of 3D integration on such DNN accelerators on area, power and performance, as well as explore the use of monolithically integrated TFT switches to implement scalable, non-regular interconnect.